The invention relates to semiconductor circuits and more particularly to circuits and methods used to bias voltage controlled oscillators.
Voltage controlled oscillators are electronic circuits that are used to control an output oscillation frequency as a function of input voltage. Voltage controlled oscillators are used in many applications including function generators and phase lock loops. For example, function generators use voltage controlled oscillators to repetitively and reliably sweep the frequency of an output waveform between an upper and a lower limit. Phase lock loops use voltage controlled oscillators to match the frequency and phase of an input signal with a reference signal by raising or lowering the frequency of the voltage controlled oscillator until it is matched to the reference signal. In the prior art, voltage controlled oscillators are typically biased by a constant current that is generated with a voltage source and transistor or by a constant transconductance (gm) biasing circuit as illustrated in FIG. 1.
FIG. 1 is an illustration showing a prior art voltage controlled oscillator (VCO) 105 that is biased with a constant transconductance (gm) biasing circuit 110. VCO 105 includes a first transistor 112, a first inductor 114, a second inductor 116, a second transistor 118, a third transistor 120, and a capacitor 122. The first transistor 112 is a PMOS transistor with its source and body coupled to the voltage bus held at voltage VDD, its drain coupled to both the first inductor 114 and the second inductor 116, and its gate coupled to the constant gm biasing circuit 110. First inductor 114 has a first end coupled to the drain of first transistor 112 and a second end coupled to both the drain of second transistor 118 and the gate of third transistor 120. Similarly, second inductor 116 has a first end coupled to the drain of first transistor 112 and a second end coupled to both the drain of third transistor 120 as well as the gate of second transistor 118. Both second transistor 118 and third transistor 120 have their sources coupled to ground. Capacitor 122 is connected between one end of the first inductor 112 and one end of the second inductor 114.
The constant gm biasing circuit 110 includes a fourth transistor 132, a fifth transistor 134, a sixth transistor 136, a seventh transistor 138 and resistor 140. Fourth transistor 132 is a PMOS transistor with its source and body also coupled to the voltage bus held at voltage VDD, its drain coupled to transistor 136, and its gate coupled to the transistor 134. Fifth transistor 134 is a PMOS transistor with its source and body coupled to the voltage bus held at voltage VDD, its drain coupled to transistor 138, and its gate coupled to the transistor 132. The gates of both transistor 132 and transistor 134 are coupled to the gate of first transistor 112 of the VCO 105 at point A. Sixth transistor 136 is an NMOS transistor with its source coupled to a resistor 140, its drain coupled to transistor 132, and its gate coupled to both transistor 138 and the bypass loop used for generating a mirror current. Seventh transistor 138 is an NMOS transistor with its source and body coupled to ground, its drain coupled to both transistor 134 and the bypass loop used to generate the mirror current. The resistor 140 is grounded.
As described above, the prior art constant gm biasing circuit 110 utilizes thin gate NMOS and PMOS devices. The biasing current generated by the constant gm biasing circuit 110 is dictated by the square law shown in equation (1) below.
                    I        =                  1                      2            ⁢                          μ              n                        ⁢                          Cox              ⁡                              (                                  W                  /                  L                                )                                      ⁢                          R              eq              2                                                          (        1        )            The equivalent resistance Req is the resistance seen by ΔVgs of the constant gm circuit where Vgs is the voltage between the gate and source of the transistors characterized as thin gate NMOS and PMOS devices.
Although conventional bandgap biasing has worked in the past for biasing VCO circuit 105, it is unable to meet the stringent requirements for low noise and low power consumption demanded by modern VCO core biasing applications. Conventional bandgap biasing is inadequate because bandgap reference circuits require larger voltage headroom. For example, a PNP transistor requires a base emitter voltage VBE of approximately 0.8 volts which is more than one-half of the typical 1.5 volt power supply requirement. When the bandgap biasing circuit is used with a regulated power supply that outputs approximately 1.5 volts, the current mirror suffers from tight voltage headroom and low voltage saturation VDSAT causing higher noise. This higher noise does not meet modern stringent requirements. Moreover, the high base resistance of PNP transistors contributes to the high noise in the bandgap reference voltage. Another source of noise can be from the power supply where noise frequency can be amplified by a device such as a VCO that has a low power supply rejection ratio (PSRR). Since the PSRR measures how well a device rejects the noise in the power supply line, a low PSRR is an indication that the VCO will be noisy.
Another problem with biasing the VCO with the constant gm biasing circuit 110, as illustrated in FIG. 1, is that it overcompensates required VCO swing due to variations in temperature. On the other hand, if the VCO is biased using a constant current rather than the constant gm biasing circuit 110, then an increase in temperature may result in lower VCO swing. affect the bias on the VCO. In addition, resistor 140 is subject to process variations from chip to chip, which will vary the gm bias.
Therefore, it would be desirable to provide a system and method to bias a voltage controlled oscillator that is not affected by variations in temperature and can operate under low power consumption requirements as well as low noise requirements and have a high power supply rejection ratio (PSRR).